RISCy Business: RISC-V CPU in Logisim

Oct 2025

Description

Designed and implemented a pipelined 32-bit RISC-V CPU in Logisim for a computer architecture course. The CPU supports 36 instructions and features a 2-stage pipeline architecture. The system includes a compiler that converts RISC-V assembly code into Logisim programs and simulates CPU behavior, demonstrating instruction execution, data flow, and pipeline operation. Partners: Aditya Anantaraman

Technologies

Digital Logic Design

Computer Architecture

RISC-V

Logisim

Gallery

Complete CPU datapath implementation

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RISC-V instruction (left) and compiled Logisim program (right)

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32-register register file (Regfile) implementation

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Control logic circuit design

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Arithmetic Logic Unit (ALU) implementation